1. Field of the Invention
The present invention relates to a Metal-Insulator-Semiconductor (MIS) type semiconductor device including an insulated gate field effect transistor (IG FET), in which the ohmic contact with the semiconductor substrate is provided on the surface of the semiconductor chip, and to a semiconductor integrated circuit comprising such a semiconductor device, as well as to a process for producing such a semiconductor device.
The term semiconductor chip used herein designates a semiconductor integrated circuit which is included in a semiconductor wafer.
The term semiconductor wafer used herein designates a piece of a semiconductor single crystal on which the various elements of a semiconductor integrated circuit are produced.
The term semiconductor substrate used herein designates a piece of a semiconductor single crystal.
2. Description of the Prior Art
In most of the semiconductor devices which include an N channel, Si-gate-MIS field effect transistor, the ohmic contact is provided on the backside of the semiconductor substrate, i.e. the backside of the semiconductor chip. Since the MIS transistor includes a thick field insulating film on the top part of the semiconductor wafer, it is necessary to form a window in the thick insulating film, in order to employ a conventional electrode structure for the ohmic contact in the MIS transistor. The formation of the electrode therefore causes the production of the semiconductor wafer to become considerably complicated and decreases the density of the integrated semiconductor circuit. It has consequently been difficult to provide the ohmic contact with the semiconductor substrate on the top side of the semiconductor chip.
The semiconductor integrated circuit having an MIS field effect transistor (FET) shown in FIG. 1 includes a P type silicon (Si) wafer 10. On the surface of the Si wafer 10, the N.sup.+ type regions 11 and 12 for source and drain of the MIS FET are formed. These N.sup.+ type regions are defined by the field insulating film 13, gate polycrystalline Si layer 14 and gate insulating film 15. Namely, in order to produce the N.sup.+ type regions, an N type impurity is introduced into the substrate using the Si layer 14 and the insulating films 13 and 15 as a mask. The N type impurity may be diffused into the substrate from the phospho-silicate glass (PSG) film 16 on the wafer so as to form the N.sup.+ type regions 11 and 12. In electrode windows of the PSG film 16 on the N.sup.+ type regions 11 and 12, a source electrode 17 and a drain electrode 18, which are usually composed of aluminum (Al) layers, are formed and ohmically contacted with the source region 11 of the drain region 12, respectively.
In such an MIS type integrated circuit, the back gate bias technique is very important for attaining the desired characteristics of the MIS FET. The back gate bias means a backward bias of PN junctions between the P type region of the substrate 10 and the N.sup.+ type regions of source and drain 11 and 12, which is achieved by an application of a predetermined amplitude of negative voltage to the P type region of the substrate 10 against the source region 11. In a P channel type MIS FET, of course, the polarity of the bias voltage is just the opposite of the above-mentioned relationship. The back gate bias provides an increase of the gate threshold voltage (Vth) of the MIS FET and a decrease of the capacitance of the PN junction between the P type Si substrate and the N.sup.+ type regions, which capacitance impedes the operating speed of the integrated circuit.
According to the prior art, a substrate electrode 19 for applying a back gate bias is generally formed on the backside surface of the substrate 10 because it is difficult to form a contact window in the PSG film 16 and the thick field insulating film 13, and to form the substrate electrode in the window. When the substrate electrode is formed on the backside surface of the substrate, it is difficult to produce the package structure of the integrated circuit, and the wiring structure between the electrodes of the semiconductor chip and outer leads of the package.
Furthermore, it is sometimes desired to connect the source electrode 17 to the P type Si substrate 10 to eliminate the back gate bias effect. However, the connection between the source electrode 17 and the substrate electrode 19 is difficult to accomplish by a simple wiring and packaging structure in the prior art.